> It sounds like you are coming up against write-posting.
> All reads happen immediately to a mmio section.
> All writes are delayed until the next read.
> So, to write a value, do the following:
> write the value to location X
> read the value back from location X
Unfortunately for me, devmem2 does exactly that. Read/modify/write followed by readback. Pretty much the same as I do with the kernel module, which works...
> To write two values, do the following:
> write a value to location X
> write a value to location Y
> read a value from either location X or location Y.
>
> This is all standard PCI programming, not linux specific.
Thanks James.
Mea culpa - it's been flipping years since I last wrote PCI drivers (and that was for LynxOS)!
Since writing that draft, I've now found what the problem is - or at least, a solution: Adding an msync() call in immediately after the write in devmem2 causes the writes to take place. Now, given this code is in use wordwide without that modification, does this suggest the mmu is misconfigured?
Peter
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